Individual Memory Cell PA0 Collection of Individual Cells PA0 Row Decoder PA0 Selecting Column After Row is Selected PA0 One Type of Decoder PA0 Disadvantages
FIG. 1 illustrates a memory cell. To store a DATA signal in the cell, first pull both the SELECT- and the WRITE lines HIGH, to thereby cause AND gates 3 and 6 to allow the DATA signal to reach the latch 9.
If the DATA signal is a ONE, the resulting state of the latch is shown in FIG. 2: the S-input receives a ONE and the R-input receives a ZERO. With these inputs, the flip-flop is driven into the "set" state, in which output X produces a ONE and output X produces a ZERO. Output X is taken as the stored value, and output X is ignored (in the present context). Thus, the "set" state stores a ONE.
Conversely, if the DATA signal is a ZERO, the resulting state of the flip-flop is shown FIG. 3: the S-input receives a ZERO and the R-input receives a ONE. With these inputs, the latch is driven into the "reset" state, in which output X produces a ZERO and output X produces a ONE. The "reset" state stores a ZERO (at output X).
The SELECT in FIG. 1 also controls whether the stored data (at output X of the latch 9) reaches the OUTPUT. That is, if the SELECT line is ZERO, AND gate 12 prevents the data at output X from reaching the OUTPUT. Conversely, if the SELECT line is ONE, AND gate transmits the data from output X to the OUTPUT.
The memory cell of FIG. 1 is indicated by the symbol 14 shown at the bottom of that Figure. A collection of these individual cells 14 can form a Random Access Memory (RAM), as indicated in FIG. 4. The RAM is the 16-to-1 type: it contains 16 cells, each of which stores one bit. The cells are arranged into four rows and four columns.
To retrieve a bit from the RAM, a ROW DECODER 15 is given a two-bit address word on lines 18, and selects the row of cells indicated by the ADDRESS word. For example, when the ADDRESS word A.sub.1 A.sub.0 equals 00, the decoder pulls SELECT LINE 00 HIGH. (The effect of the SELECT LINE upon the individual cells was explained in connection with FIG. 1.) When SELECT LINE 00 is HIGH, all of the cells in row 00 deliver their contents to the respective OUTPUT lines 24-27.
Similarly, when the ADDRESS word is 01, the DECODER actuates the SELECT line 01, causing all cells in row 01 to deliver their contents to the respective output lines 24-27. The SELECT lines 10 and 11 operate in the same way.
Once a row of cells has been actuated, one of the four output lines 24-27 must be selected. The selection is done by a COLUMN DECODER 21, which selects one of the output signals, and suppresses the rest, by means of the AND gates 30A-30D. For example, as shown in FIG. 5, if the address input to the COLUMN DECODER 21 is 11, then column 11 is selected, thus delivering the output of the shaded cell to the OUTPUT, as indicated by dashed path 36.
FIG. 6 illustrates how one type of DECODER works. When the address input A.sub.1 A.sub.0 is 00, all AND gates (with one exception) receive at least one ZERO, and consequently produce a ZERO as output. The exception is AND gate 39, which receives two ONEs, because of INVERTERS 41. Thus, only AND gate 39 produces a ONE as output.
When this output connects to SELECT line 00, all cells in row 00 become selected. Similarly, when the address input to the decoder is 01, AND gate 42 alone receives two ONEs, and it solely produces a ONE as output, on SELECT LINE 01. SELECT LINES 10 and 11 are actuated in similar ways.
This particular type of cell selection has two disadvantages when high-speed operation is desired. First, the COLUMN DECODER 21 (contained in dashed block 42 in FIG. 4) delays the data travelling from a cell to the OUTPUT. That is, the data leaving a cell must pass through AND gates 30A-30D and OR gate 33. These gates delay the data.
A second disadvantage is that, when a new address is applied to the DECODERS in FIG. 4, there is no longer any certainty that the data present at the OUTPUT of the OR gate 33 represents the data contained in the previously selected cell, namely, the shaded cell in FIG. 5. That is, when DECODER 21 receives a new address, it activates one of its four output lines, almost immediately, thereby selecting one of the output lines 24-27. The OUTPUT data produced by OR gate 33 is no longer valid.
Therefore, two disadvantages are (1) a relatively long access time (because the data must travel through the COLUMN DECODER) and (2) a short output hold time (because the data becomes corrupted as soon as a new address is applied to the COLUMN DECODER.)